industrial temperature range idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity 1 march 2006 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ?2006 integrated device technology, inc. dsc-4582/3 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ?v cc = 2.5v 0.2v ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? available in tssop package functional block diagram applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems drive features: ? high output drivers: 24ma ? suitable for heavy loads idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity generators/ checkers and bus-hold description: this 18-bit universal bus transceiver is built using advanced dual metal cmos technology. the alvch16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. the device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. the alvch16901 features independent clock (clkab or clkba), latch-enable (leab or leba), and dual 9-bit clock enable ( clkenab or clkenba ) inputs. it also provides parity-enable ( sel ) and parity-select (odd/ even ) inputs and separate error-signal ( erra and errb ) outputs for checking parity. the direction of data flow is controlled by oeab and oeba . when sel is low, the parity functions are enabled. when sel is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver. the alvch16901 has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. the alvch16901 has ?bus-hold? which retains the inputs? last state whenever the input bus goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors. 1 clkenab 2 clkenab leab oeab odd/even 1 a 1 - 1 a 8 sel b-port parity generate and check a data 2 a-port parity generate and check b data 18-bit storage clkab 1 apar 1 errb 2 a 1 - 2 a 8 2 apar 2 errb 1 b 1 - 1 b 8 1 bpar 1 erra 2 b 1 - 2 a 8 2 bpar 2 erra oeba clkba 1 clkenba 2 clkenba leba 18-bit storage 18 18 18 18 q a q b 2 2 1 32 3 30 5 61 28 36 34 31 63 64 33 62 29 37 35 60 4
industrial temperature range 2 idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity tssop top view pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, 50 ma v i < 0 or v i > v cc i ok continuous clamp current, v o < 0 ?50 ma i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c out i/o port capacitance v in = 0v 7 9 pf capacitance (t a = +25c, f = 1.0mhz) 1 clkenab leab clkab 1 erra v cc gnd 1 a 1 v cc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 56 57 58 59 60 61 62 63 64 1 v cc gnd v cc gnd gnd 25 26 27 28 40 39 38 37 2 bpar clkba 2 clkenab sel 29 30 31 32 36 35 34 33 2 clkenba 1 apar gnd 1 clkenba leba 1 errb 1 bpar gnd 1 a 2 1 a 3 1 a 4 1 a 5 1 a 6 1 b 1 1 b 2 1 b 3 1 b 4 1 b 5 1 b 6 1 a 7 1 a 8 2 a 1 1 b 7 1 b 8 2 b 1 2 a 2 2 b 2 2 a 3 2 b 3 gnd gnd 2 b 4 2 b 5 2 a 4 2 a 5 2 a 6 2 a 8 2 a 7 2 b 6 2 b 7 2 b 8 oeab 2 erra 2 apar odd/even 2 errb oeba note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os. pin names description oeab a-to-b output enable input (active low) oeba b-to-a output enable input (active low) leab a-to-b latch enable input leba b-to-a latch enable input xclkenab a-to-b 9-bit clock enables xclkenba b-to-a 9-bit clock enables clkab a-to-b clock input clkba b-to-a clock input xerra a error-signal outputs xerrb b error-signal outputs xapar a port parities xbpar b port parities odd/ even parity select input sel parity enables x a x a-to-b data inputs or b-to-a 3-state outputs (1) x b x b-to-a data inputs or a-to-b 3-state outputs (1) pin description
industrial temperature range idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity 3 function table (1,2) inputs outputs clkenab oeab leab clkab xax xbx xh x xxz xlh xll xlh xhh hll xxb (3) lll ll lll hh lll lxb (3) lll hxb (4) notes: 1. h = high voltage level l = low voltage level x = don?t care = low-to-high transition 2. a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, and clkenba . 3. output level before the indicated steady-state conditions were established. 4. output level before the indicated steady-state conditions were established, provided that clkab was low before leab went low. parity enable inputs sel oeba oeab operation or function l h l parity is checked on port a and is generated on port b. l l h parity is checked on port b and is generated on port a. l h h parity is checked on port b and port a. l l l parity is generated on port a and b if device is in ff mode. h l l parity functions are q a data to b, q b data to a h l h disabled; device acts as q b data to a h h l a standard 18-bit q a data to b h h h registered transceiver. isolation parity inputs outputs of inputs of inputs sel oeba oeab odd/ even a1- ? ? ? ? ? a8 = h b1? ? ? ? ? ? b8 = h xapar xbpar xapar xerra xbpar xerrb l h l l 0, 2, 4, 6, 8 n/a l n/a n/a h l z l h l l 1, 3, 5, 7 n/a l n/a n/a l h z l h l l 0, 2, 4, 6, 8 n/a h n/a n/a l l z l h l l 1, 3, 5, 7 n/a h n/a n/a h h z l l h l n/a 0, 2, 4, 6, 8 n/a l l z n/a h l l h l n/a 1, 3, 5, 7 n/a l h z n/a l l l h l n/a 0, 2, 4, 6, 8 n/a h l z n/a l l l h l n/a 1, 3, 5, 7 n/a h h z n/a h l h l h 0, 2, 4, 6, 8 n/a l n/a n/a l h z l h l h 1, 3, 5, 7 n/a l n/a n/a h l z l h l h 0, 2, 4, 6, 8 n/a h n/a n/a h h z l h l h 1, 3, 5, 7 n/a h n/a n/a l l z l l h h n/a 0, 2, 4, 6, 8 n/a l h z n/a l l l h h n/a 1, 3, 5, 7 n/a l l z n/a h l l h h n/a 0, 2, 4, 6, 8 n/a h h z n/a h l l h h n/a 1, 3, 5, 7 n/a h l z n/a l l h h l 0, 2, 4, 6, 8 0, 2, 4, 6, 8 l l n/a h n/a h l h h l 1, 3, 5, 7 1, 3, 5, 7 l l n/a l n/a l l h h l 0, 2, 4, 6, 8 0, 2, 4, 6, 8 h h n/a l n/a l l h h l 1, 3, 5, 7 1, 3, 5, 7 h h n/a h n/a h l h h h 0, 2, 4, 6, 8 0, 2, 4, 6, 8 l l n/a l n/a l l h h h 1, 3, 5, 7 1, 3, 5, 7 l l n/a h n/a h l h h h 0, 2, 4, 6, 8 0, 2, 4, 6, 8 h h n/a h n/a h l h h h 1, 3, 5, 7 1, 3, 5, 7 h h n/a l n/a l l l l l n/a n/a n/a n/a pe (1) zpe (1) z l l l h n/a n/a n/a n/a po (2) zpo (2) z notes: 1. parity output is set to the level so that the specific bus side is set to even parity. 2. parity output is set to the level so that the specific bus side is set to odd parity.
industrial temperature range 4 idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input high current v cc = 3.6v v i = v cc ?? 5a i il input low current v cc = 3.6v v i = gnd ? ? 5a i ozh high impedance output current v cc = 3.6v v o = v cc ?? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v ? 0.1 40 a i cch v in = gnd or v cc i ccz i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 750 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c note: 1. typical values are at v cc = 3.3v, +25c ambient. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? 45 ? ? a i bhl v i = 0.7v 45 ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity 5 operating characteristics, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 22 27 pf c pd power dissipation capacitance outputs disabled 5 8 note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55
industrial temperature range 6 idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit f max 125 ? 125 ? 125 ? m h z t plh propagation delay 1 5.2 ? 4.8 1 4.4 ns t phl xax to xbx or xbx to xax t plh propagation delay 2 8.9 ? 7.6 2 6.7 ns t phl xax to xbpar or xbx to xapar t plh propagation delay 1 5.7 ? 5.2 1 4.7 ns t phl xapar to xbpar or xbpar to xapar t plh propagation delay 2 9.7 ? 8.7 2 7.5 ns t phl xapar to x erra or xbpar to x errb t plh propagation delay 1.5 8.7 ? 7.9 1.5 6.8 ns t phl odd/ even to x errb or x erra t plh propagation delay 1.5 8.3 ? 7.6 1.5 6.5 ns t phl odd/ even to xapar or xbpar t plh propagation delay 1 6.1 ? 5.9 1 5.1 ns t phl sel to xapar or xbpar t plh propagation delay 1 6 ? 5.5 1 4.8 ns t phl leba to xax or leab to xbx t plh propagation delay 1.5 6.7 ? 6 1.5 5.3 ns t phl leba to xapar or leab to xbpar (parity feed through) t plh propagation delay 2.5 9.8 ? 8.3 2 7.4 ns t phl leba to xapar or leab to xbpar (parity generated) t plh propagation delay 2.5 9.9 ? 8.5 2 7.5 ns t phl leba to x errb or leab to x erra t plh propagation delay 1 6.4 ? 5.8 1 5.1 ns t phl clkba to xax or clkab to xbx t plh propagation delay 1.5 7.1 ? 6.3 1.5 5.6 ns t phl clkba to xapar or clkab to xbpar(parity feed through) t plh propagation delay 2.5 10.2 ? 8.7 2 7.7 ns t phl clkba to xapar or clkab to xbpar(parity generated) t plh propagation delay 2.5 10.5 ? 8.9 2 7.9 ns t phl clkba to x errb or clkab to x erra switching characteristics (1)
industrial temperature range idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity 7 v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit t pzh output enable time 1.4 6.3 ? 6.1 1 5.3 ns t pzl oeab or oeba to xbx, xbpar or xax, xapar t pzh output enable time 1.4 6.2 ? 5.5 1 4.9 ns t pzl oeab or oeba to x erra or x errb t pzh output enable time 1.4 6.7 ? 6.5 1 5.5 ns t pzl sel to x erra or x errb t phz output disable time 1.3 6.1 ? 5.2 1.5 4.9 ns t plz oeab or oeba to xbx, xbpar or xax, xapar t phz output disable time 1.3 7.3 ? 6.5 1 5.7 ns t plz oeab or oeba to x erra or x errb t phz output disable time 1.3 6.4 ? 5.4 1.5 4.9 ns t plz sel to x erra or x errb t su set-up time, high or low, 1.9 ? 2 ? 1.7 ? ns xax, xapar or xbx, xbpar before clk t su set-up time, high or low, 2.1 ? 2.1 ? 1.7 ? ns x clkenab or x clkenba before clk t su set-up time, high or low, 1.4 ? 1.3 ? 1.2 ? ns xax, xapar or xbx, xbpar before le t h hold time, high or low, 0.4 ? 0.4 ? 0.5 ? ns xax, xapar or xbx, xbpar after clk t h hold time, high or low, 0.5 ? 0.5 ? 0.7 ? ns x clkenab or x clkenba after clk t h hold time, high or low, 0.9 ? 1.1 ? 0.9 ? ns xax, xapar or xbx, xbpar after le t w pulse width leab or leba high 3 ? 3 ? 3 ? ns t w pulse width clkab or clkba high or low 3 ? 3 ? 3 ? ns t sk (o) output skew (2) ? ????500 ps switching characteristics (continued) (1) notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2 skew between any two outputs of the same package and switching in the same direction.
industrial temperature range 8 idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity open v load gnd v cc pulse generator d.u.t. 500 500 c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 1.0mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range idt74alvch16901 3.3v cmos 18-bit universal bus transceiver with parity 9 ordering information xx alvc xxx xx package device type temp. range pa pag 16 74 thin shrink small outline package tssop - green 18-bit universal bus transceiver with parity generators/checkers -40c to +85c x xxx family bus-hold 901 bus-hold double-density, 24ma h corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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